40G QSFP+ Module Package Structure Design
The 40G QSFP+ SR4 optical module is divided into two parts: transmitting and receiving. The transmitting part is mainly composed of a 4-way 850nmVCSEL array and its driver chip, and the receiving part is mainly composed of a 4-way photodetector (PD) array and a trans-impedance amplifier TIA. First, the VCSEL and PD were assembled on the Si substrate carrier by flip-chip bonding (FC) packaging process, and then the driver and TIA were pasted on another substrate, and the Si substrate carrier with VCSEL and the driver were bonded to The VCSEL and the driver are interconnected together, the PD and the TIA are interconnected by the same packaging method, and finally the chip is connected to the packaging substrate through the packaging process.
40G QSFP+ Module Power Integrity Design
The driver and TIA are high-speed digital chips. In the working state, the switching of the gate circuit causes the change of the chip supply current. If there is a large parasitic inductance in the current loop, the current change will cause the voltage to collapse, resulting in the power plane or the ground plane. voltage difference thus producing transient synchronous switching noise.
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In the cavity formed by the power supply and the ground plane, the transient synchronous switching noise is used as the excitation source to further excite the noise in the cavity, and the noise will harm the shared or adjacent chip power supply network through structures such as parasitic capacitance, resulting in the formation of inter-chip power supply network crosstalk, affecting the normal working state of adjacent chips. In the design of power integrity (PI), on the one hand, it is necessary to reduce the impedance of the respective power supply networks of the two and reduce the return inductance to suppress the transient synchronous switching noise; The noise in the system increases the isolation of the power supply network between chips.
The commonly used power filter network is usually composed of independent surface-mounted capacitors, inductors and resistors, which occupy a large area on the board and because of large parasitic parameters, the filter frequency range is below 2GHz. Moreover, for an electronic system with a channel rate of 10Gbps, the fundamental frequency of the channel transmission signal is 5GHz, and its effective harmonic component can reach about 15GHz. These high-frequency signals are coupled to the power supply through the signal vias on the substrate and the parasitic capacitance of the power plane. In the system, it becomes high-frequency power supply noise. Under the small package size, the high-frequency noise cannot be attenuated in time and becomes a source of harm.
In order to design and manufacture a miniaturized, low-cost transceiver integrated 40G optical module, a novel embedded capacitor filter (ECF) is used to replace the traditional filter network composed of surface mount capacitors, resistors, and inductors. , which not only saves the surface area of the package substrate occupied by the surface mount filter, but also realizes ultra-wideband filtering because of the small parasitic parameters of the embedded filter, which greatly improves the performance of the 40G optical module power supply system.
The 40G QSFP+ optical module developed in this paper. By adopting the embedded substrate technology, the miniaturization of the optical module is realized, the manufacturing cost is reduced, the reliability of the module is improved, and the crosstalk of the circuit system of the receiving and transmitting parts of the module is reduced. The 40GBASE-SR4 supports InfiniBand QSFP electrical interface and 12-way MPO optical interface hot-swappable and can reach 100m transmission distance using OM3 fiber optic ribbon. The developed 40G QSFP+ optical module meets the needs of high-speed and large-data signal transmission in high-end routers, supercomputers, and blade server rooms, and provides a low-cost and high-performance solution for the development of 40Gbps Ethernet.